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general description the max11080 is a battery-pack fault-monitor ic capa- ble of monitoring up to 12 lithium-ion (li+) battery cells. this device is designed to provide an overvolt- age or undervoltage fault indication when any of the cells cross the user-selectable threshold for longer than the set program-delay interval. the overvoltage levels are pin selectable from +3.3v to +4.8v in 100mv increments, and have a guaranteed accuracy of ?5mv over the entire temperature range. the under- voltage level is also user selectable from +1.6v to +2.8v in 200mv increments. these levels are guaran- teed to ?00mv over the entire temperature range. undervoltage detection can be disabled as one of the user-configuration options. the max11080 has a built-in level-shifter that allows up to 31 max11080 devices to be connected in a daisy- chain fashion to reduce the number of interface signals needed for large stacks of series batteries. each cell is monitored differentially and compared to the overvolt- age and undervoltage thresholds. when any of the cells exceed this threshold for longer than the set program delay interval, the max11080 inhibits the heartbeat sig- nal from being passed down the daisy chain. built-in comparator hysteresis prevents threshold chattering. the max11080 is designed to be the perfect comple- ment to the max11068 high-voltage measurement ic for redundant fault-monitoring applications. this device is offered in a 9.7mm x 4.4mm, 38-pin tssop package with 0.5mm pin spacing. the package is lead-free and rohs compliant with an extended operating tempera- ture range of -40? to +105?. applications high-voltage, multicell-series-stacked battery systems electric vehicles hybrid electric vehicles electric bikes high-power battery backup solar cell battery backup super-cap battery backup features up to 12-cell li+ battery voltage fault detection operation from 6.0v to 72v pin-selectable overvoltage threshold from +3.3v to +4.8v in 100mv increments ?5mv overvoltage-detection accuracy pin-selectable undervoltage threshold from +1.6v to +2.8v in 200mv increments ?00mv undervoltage-detection accuracy 300mv over/undervoltage-threshold detection hysteresis programmable delay time of alarm detection from 3.0ms to 3.32s with an external capacitor daisy-chained alarm and shutdown functions with heartbeat status signal up to 31 devices can be connected ultra-low-power dissipation operating-mode current drain: 80 a shutdown-mode current: 2 a wide operating temperature range from -40? to +105? (aec-q100 type 2) 9.7mm x 4.4mm, 38-pin tssop package lead(pb) free and rohs compliant max11080 12-channel, high-voltage battery-pack fault monitor ________________________________________________________________ maxim integrated products 1 ordering information 19-4584; rev 0; 5/09 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. + denotes a lead(pb)-free/rohs-compliant package. /v denotes an automotive qualified part. part temp range pin-package MAX11080GUU+ -40 c to +105 c 38 tssop MAX11080GUU/v+ -40 c to +105 c 38 tssop pin configuration appears at end of data sheet.
max11080 12-channel, high-voltage battery-pack fault monitor 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (t a = t min to t max , unless otherwise noted. v dcin = v gnd u = +6.0v to +72v, typical values are at t a = +25?, unless otherwise specified from -40? to +105?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. hv, vdd u , gnd u , dcin to agnd.........................-0.3v to +80v hv to dcin and c12 ................................................-0.3v to +6v c2?12 to agnd ....................................-0.3v to (v dcin + 0.6v) cn+1 to cn, where n = 2 to 12...............................-0.3v to +80v c1 to c0 ...................................................-0.3v to +20v (note 1) c1 to agnd ..............................-0.3v to (v dcin + 0.6v) (note 2) c0 to agnd...........................................................-0.3v to +0.9v shdn , v aa to agnd ................................................-0.3v to +4v vdd u to gnd u .........................................................-0.3v to +6v ovsel_, uvsel_, topsel to agnd ......-0.3v to (+v aa + 0.3v) cd, alrm l to agnd ...............................-0.3v to (+v aa + 0.3v) alrm u to gnd u ...................................-0.3v to (+vdd u + 0.3v) cp+ to agnd ...........................(gnd u - 0.3v) to (vdd u + 0.3v) cp- to agnd...........................................-0.3v to (gnd u + 0.3v) cp- to vdd u .......................................................................+0.3v esd rating c_, ref, v aa , vdd u gnd u , dcin, shdn , cp+, cp-, hv, ovsel_, uvsel_, topsel, alrm u , alrm l , agnd, cd .............................. ?kv (human body model, note 3) continuous power dissipation (t a = +70?) 38-pin tssop (derating 15.9mw/? above +70?) .........................1095.9mw operating temperature range .........................-40? to +105? storage temperature range .............................-55? to +150? junction temperature (continuous) .................................+150? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units c_ inputs common-mode input range vc xin any two inputs cn to cn+1 for full threshold accuracy (note 4) 1.5 72 v input current ic xin v cell = 3.0v -1 0.05 +1 ? overvoltage threshold v ov +3.3 +4.8 v overvoltage-threshold accuracy 5 25 mv undervoltage threshold v uv +1.6 +2.8 v undervoltage-threshold accuracy 20 100 mv comparator hysteresis v hys 300 mv cd pin cd current i cd v cd = 0.4v 4.35 6.1 7.65 ? cd trip voltage v cd internal at comparator 1.23 v delay-time accuracy excluding c dly variation 20 % status/control port shutdown disable ( shdn high voltage) shdn /v ih 2.1 v shutdown asserted ( shdn low voltage) shdn /v il 0.6 v note 1: the c1 to c0 differential input path is tolerant to 80v as long as the shdn pin is deasserted. note 2: the c1 input is tolerant to a maximum v dcin + 0.6v. if shdn is asserted, 20v is the maximum rating. note 3: human body model to specification mil-std-883 method 3015.7.
max11080 12-channel, high-voltage battery-pack fault monitor _______________________________________________________________________________________ 3 electrical characteristics (continued) (t a = t min to t max , unless otherwise noted. v dcin = v gnd u = +6.0v to +72v, typical values are at t a = +25?, unless otherwise specified from -40? to +105?.) parameter symbol conditions min typ max units vdd u output high vdd u v oh output voltage of vdd u after the 20k ? /200k ? resistor-divider to shdn gnd u + 2.4 v vdd u output low vdd u v ol output voltage of vdd u after the 20k ? /200k ? r esi stor - d i vi d er for s h dn gnd u + 0.3 v alrm l output-voltage high alrm l v oh i source = 150? 2.4 v alrm l output-voltage low alrm l v ol i sink = 150? 0.6 v alrm u input-voltage high alrm u v ih daisy-chained alrm u signal as coupled through a 3.3nf high-voltage capacitor and a 150k ? resistor as referred to gnd u gnd u + 2.1 v alrm u input-voltage low alrm u v il daisy-chained alrm u signal as coupled through a 3.3nf high-voltage capacitor and a 150k ? resistor as referred to gnd u gnd u + 0.9 v alarm voltage output ?eartbeat frequency alrm l f out heartbeat clock rate with no alarm condition 4032 4096 4157 hz alarm voltage output duty cycle heartbeat clock rate with no alarm condition 49.0 51.0 % linear regulator (v aa ) input voltage range v dcin 672v output voltage v aaout 6v < v dcin < 72v, i load = 0 3.0 3.3 3.6 v short-circuit current i aa s h ort c ir c u it v aa = 0, 6v < v dcin < 36v 50 ma v aareset falling v aa 2.8 v aavalid rising v aa 3.0 v power-on-reset trip level (note 4) v aahys hysteresis on rising v aa 37 mv thermal shutdown t shut rising temperature +145 ? power-supply requirements (dcin) operating mode, shdn = 1, 12 battery cells, alarm inactive, v dcin = v gnd u = 36v 35 40 current consumption i dcin shutdown mode, shdn = 0, 12 battery cells, v dcin = v gnd u = 36v 1.3 2 ? i gnd u operating mode shdn = 1, battery cells, alarm inactive, v dcin = v gnd u = 36v 35 40 ? logic inputs and outputs v ih uvsel0/uvsel1/uvsel2, topsel vaa - 0.1 threshold setting v il ovselo/ovsel1/ovsel2/ovsel3 0.1 v note 4: guaranteed by design and not production tested.
max11080 12-channel, high-voltage battery-pack fault monitor 4 _______________________________________________________________________________________ typical operating characteristics (t a = +25?, unless otherwise noted.) undervoltage set threshold vs. temperature max11080 toc01 temperature ( c) undervoltage set threshold (v) 80 0 -20 60 40 1.59 1.60 1.61 1.56 1.57 1.58 1.62 1.63 1.64 1.55 -40 20 100 1.6v set point max mean min cd current distribution max11080 toc02 cd pin current ( a) device count 5.6 6.6 6.0 5.8 6.4 10 15 20 5 25 30 35 0 5.4 6.2 cd charging current vs. temperature max11080 toc03 temperature ( c) cd current ( a) 80 0 -20 60 40 6.00 6.01 6.02 5.97 5.98 5.99 6.03 5.96 -40 20 100 v cd = 0.4v dcin supply current vs. v dcin max11080 toc04 v dcin (v) i dcin ( a) 50 80 40 30 40 50 60 30 70 20 020 6070 10 4.8v overvoltage threshold v cell = v dcin /12 t a = +105 c t a = +25 c t a = -40 c gnd u supply current vs. gnd u voltage max11080 toc05 v gndu (v) i gndu ( a) 50 80 40 30 25 30 35 20 40 45 50 55 15 020 6070 10 t a = +105 c t a = +25 c t a = -40 c overvoltage clear threshold vs. temperature max11080 toc06 temperature ( c) overvoltage clear threshold (v) 80 0 -20 60 40 4.51 4.52 4.53 4.48 4.49 4.50 4.54 4.47 -40 20 100 4.8v set point max mean min overvoltage set threshold vs. temperature max11080 toc07 temperature ( c) overvoltage set threshold (v) 80 0 -20 60 40 4.800 4.802 4.804 4.794 4.796 4.798 4.806 4.792 -40 20 100 4.8v set point max mean min undervoltage clear threshold vs. temperature max11080 toc08 temperature ( c) undervoltage clear threshold (v) 80 0 -20 60 40 1.90 1.92 1.84 1.86 1.88 1.94 1.82 -40 20 100 1.6v set point max mean min
max11080 12-channel, high-voltage battery-pack fault monitor _______________________________________________________________________________________ 5 pin description pin name function 1 dcin dc power-supply input. dcin supplies the internal 3.3v regulator. this pin should be connected as shown in the application diagrams. 2hv high-voltage bias. hv is biased by the output of the charge pump to provide a dc supply above the dcin level. it is used internally to bias the cell-comparator circuitry. bypass to dcin with a 1? capacitor. 3, 33 n.c. no connection 4 c12 cell 12 plus connection. top of battery module stack. 5 c11 cell 12 minus connection and cell 11 plus connection 6 c10 cell 11 minus connection and cell 10 plus connection 7 c9 cell 10 minus connection and cell 9 plus connection 8 c8 cell 9 minus connection and cell 8 plus connection 9 c7 cell 8 minus connection and cell 7 plus connection 10 c6 cell 7 minus connection and cell 6 plus connection 11 c5 cell 6 minus connection and cell 5 plus connection 12 c4 cell 5 minus connection and cell 4 plus connection 13 c3 cell 4 minus connection and cell 3 plus connection 14 c2 cell 3 minus connection and cell 2 plus connection 15 c1 cell 2 minus connection and cell 1 plus connection 16 c0 cell 1 minus connection 17 uvsel0 18 uvsel1 19 uvsel2 undervoltage threshold select 2 to 0. used to select one of eight undervoltage alarm threshold settings. the parts have internal pulldown; these pins should only be tied to v aa or agnd to set the logic state. 20 ovsel0 21 ovsel1 22 ovsel2 23 ovsel3 overvoltage threshold select 3 to 0. used to select one of 16 overvoltage alarm threshold settings. the parts have internal pulldown; these pins should only be tied to v aa or agnd to set the logic state. 24 v aa +3.3v analog supply output. bypass with a 1? capacitor to agnd. 25, 29, 30, 32 agnd analog ground. should be connected to the negative terminal of cell 1. 26 shdn active-low shutdown input. this pin completely shuts down the max11080 internal regulator and oscillators when the pin is less than 0.6v as referenced to agnd. the host controller should drive shdn for the first pack. shdn for daisy-chained modules should be connected to the lower neighboring module? vdd u through a 20k ? series resistor. 27 alrm l lower port alarm output. this output is an alarm indicator for overvoltage, undervoltage, and setup faults. the alarm signal is daisy chained and driven from the highest module down to the lowest. the alarm output is nominally a clocked ?eartbeat?signal that provides a 4khz clock when no alarm is present. the alrm l can also be configured as level signal and set to ?ow?for no alarm and ?igh?for alarm state. see the topsel function section for details. this signal swings between v aa and agnd, and is active high in the alarm state. 28 cd programmable delay time. connect a capacitor from this pin to agnd to set the hold time required for a fault condition before the alarm is set. the capacitor should be a ceramic capacitor in the 15nf to 16.5? range.
max11080 12-channel, high-voltage battery-pack fault monitor 6 _______________________________________________________________________________________ pin description (continued) pin name function 31 topsel input to indicate topmost device in the daisy chain. this pin should be connected to agnd for all devices except the topmost. for the top device, this pin should be connected to v aa . 34 alrm u upper port alarm input. this input receives the alrm l output signal from an upper neighboring module. it swings between vdd u and gnd u . 35 gnd u level-shifted upper port ground. upper port-supply return and supply input for the charge pump and hv supplies. this pin should be connected to the dcin takeoff point on the battery stack as shown in the application diagrams. 36 vdd u level-shifted upper port supply. upper port-supply output for the daisy-chained bus. this is a regulated output voltage from the internal charge pump that is level-shifted above the dcin pin voltage level. it should be bypassed with a 1? capacitor to gnd u. 37, 38 cp-, cp+ charge-pump capacitor. negative/positive input for the internal charge pump. connect a 0.01? high- voltage capacitor between cp+ and cp-.
max11080 12-channel, high-voltage battery-pack fault monitor _______________________________________________________________________________________ 7 max11080 cell comparators ldo regulator cell comparators c12 hv dcin c11 c10 cell comparators cell comparators c9 c8 cell comparators cell comparators c7 c6 cell comparators cell comparators c5 c4 cell comparators cell comparators c3 c2 cell comparators cell comparators c1 c0 agnd cd fault-state machine and control logic fault lower port alrm l shdn ovsel3 ovsel2 ovsel1 ovsel0 uvsel2 uvsel1 uvsel0 topsel upper port vdd u alrm u gnd u level shift cp+ cp- v aa fault figure 1. functional diagram
max11080 12-channel, high-voltage battery-pack fault monitor 8 _______________________________________________________________________________________ max11080 vdd u alrm u agnd cd hv dcin c3 dc 3.3nf 630v gnd u c hv 1 f 6v r2 dc 20k ? r dcin 5k ? c dcin 0.1 f 80v c dly 15nf to 16.5 f ceramic cap c dd 1 f 6v c p 0.01 f 100v gnd u gnd u gnd u d prot 5.6v smcj70 fuse c12 r13 c12 cell 12 module+ (n) module- (n) module- (n+1) bus bar bus bar c11 r12 c11 cell 11 c10 r11 c10 cell 10 c9 r10 c9 cell 9 c8 r9 c8 cell 8 c7 r8 c7 cell 7 c6 r7 c6 cell 6 c5 r6 c5 cell 5 c4 r5 c4 cell 4 c3 r4 c3 cell 3 c2 r3 c2 cell 2 c1 r2 c1 cell 1 c0 module n+1 cell stack module n+1 gnd reference module n-1 cell stack module n-1 gnd u takeoff local ground r1 dc 150k ? r shd2 20k ? r shd 200k ? shdn alrm l gnd u cp+ cp- c a 1 f 6v v aa alrm l ovsel3 ovsel2 ovsel1 ovsel0 uvsel2 uvsel1 uvsel0 topsel shdn daisy-chain bus to upper modules module n+1 isolator and control interface see text for gnd u connection options v aa jumper bank r2?r13 = 10k ? c1?c12 = 0.1 f/80v figure 2. application circuit diagram for a 12-cell system
max11080 12-channel, high-voltage battery-pack fault monitor _______________________________________________________________________________________ 9 max11080 vdd u alrm u agnd cd hv dcin c3 dc 3.3nf 630v gnd u c hv 1 f 6v r2 dc 20k ? r dcin 5k ? c dcin 0.1 f 80v c dly 15nf to 16.5 f ceramic cap c dd 1 f 6v c p 0.01 f 100v gnd u gnd u gnd u d prot 5.6v smcj70 fuse c12 r11 c10 cell 10 module+ (n) module- (n) module- (n+1) bus bar bus bar c11 c10 c9 r10 c9 cell 9 c8 r9 c8 cell 8 c7 r8 c7 cell 7 c6 r7 c6 cell 6 c5 r6 c5 cell 5 c4 r5 c4 cell 4 c3 r4 c3 cell 3 c2 r3 c2 cell 2 c1 r2 c1 cell 1 c0 module n+1 cell stack module n+1 gnd reference module n-1 cell stack module n-1 gnd u takeoff local ground r1 dc 150k ? r shd2 20k ? r shd 200k ? shdn alrm l gnd u cp+ cp- c a 1 f 6v v aa alrm l ovsel3 ovsel2 ovsel1 ovsel0 uvsel2 uvsel1 uvsel0 topsel shdn daisy-chain bus to upper modules module n+1 isolator and control interface v aa jumper bank r2?r11 = 10k ? c1?c10 = 0.1 f/80v figure 3. application circuit diagram for a 10-cell system
max11080 12-channel, high-voltage battery-pack fault monitor 10 ______________________________________________________________________________________ max11080 vdd u alrm u agnd cd hv dcin c3 dc 3.3nf 630v gnd u c hv 1 f 6v r2 dc 20k ? r dcin 5k ? c dcin 0.1 f 80v c dly 15nf to 16.5 f ceramic cap c dd 1 f 6v c p 0.01 f 100v gnd u gnd u gnd u d prot 5.6v smcj70 fuse c12 r9 c8 cell 8 module+ (n) module- (n) module- (n+1) bus bar bus bar c11 c10 c9 c8 c7 r8 c7 cell 7 c6 r7 c6 cell 6 c5 r6 c5 cell 5 c4 r5 c4 cell 4 c3 r4 c3 cell 3 c2 r3 c2 cell 2 c1 r2 c1 cell 1 c0 module n+1 cell stack module n+1 gnd reference module n-1 cell stack module n-1 gnd u takeoff local ground r1 dc 150k ? r shd2 20k ? r shd 200k ? shdn alrm l gnd u cp+ cp- c a 1 f 6v v aa alrm l ovsel3 ovsel2 ovsel1 ovsel0 uvsel2 uvsel1 uvsel0 topsel shdn daisy-chain bus to upper modules module n+1 isolator and control interface v aa jumper bank r2?r9 = 10k ? c1?c8 = 0.1 f/80v figure 4. application circuit diagram for an 8-cell system
max11080 12-channel, high-voltage battery-pack fault monitor ______________________________________________________________________________________ 11 max11068 vdd u alrm u agnd ref hv dcin dcin scl u c dcin1 c dcin2 d prot2 smcj70 d prot1 smcj70 dcin d 1 fuse c1q750 (1206) c12 r13 c12 cell 12 module+ (n) module- (n) module- (n+1) bus bar bus bar c11 r12 c11 cell 11 c10 r11 c10 cell 10 c9 r10 c9 cell 9 c8 r9 c8 cell 8 c7 r8 c7 cell 7 c6 r7 c6 cell 6 c5 r6 c5 cell 5 c4 r5 c4 cell 4 c3 r4 c3 cell 3 c2 r3 c2 cell 2 c1 r2 r1 c1 c0 cell 1 c0 thrm auxin2 auxin1 module n+1 cell stack module n+1 gnd reference module n-1 cell stack sda u gnd u cp+ cp- vdd l scl l sda l alrm l gnd l gpio1 gpio2 gpio0 v aa shdn max11080 alrm u vdd u c12 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 gnd u cp+ cp- topsel shdn cd ovsel0 alrm l isolator and control interface for first module r26 r25 r24 r23 r22 r21 r20 r19 r18 r17 r15 r16 c24 c23 c22 c21 c20 c19 c18 c17 c16 c15 c14 c13 local ground refer to each device's application reference circuits for components and values not shown on this simplified system-level schem atic. battery connector hv dcin v aa agnd uvsel1 uvsel0 uvsel2 ovsel1 ovsel2 ovsel3 r dcin2 d 2 gpio alrm l (max11080) alrm l (max11068) sda l scl l shdn figure 5. battery module system with redundant fault-detection application schematic
max11080 12-channel, high-voltage battery-pack fault monitor 12 ______________________________________________________________________________________ hv vdd u cp+ alrm u gnd u cp- dcin c12 c0 agnd c1 to c11 6v 6v 4v 4v 80v 80v 80v 6v v aa alrm l topsel shdn cd ovsel0/1/2/3 uvsel0/1/2 max11080 esd diodes figure 6. esd diode diagram detailed description figure 1 shows the functional diagram; figure 2 shows the application circuit diagram for a 12-cell system while figure 3 shows the application circuit design for a 10-cell system and figure 4 for an 8-cell system. figure 5 is the application schematic for the battery module system with redundant fault detection. architectural overview the max11080 is a battery-pack fault-monitor ic capa- ble of monitoring up to 12 li+ battery cells. this device is designed to provide an overvoltage or undervoltage alarm indicator when any of the cells cross the user- selectable threshold for longer than the configured decision delay interval. the max11080 also incorpo- rates a daisy-chain bus for use in high-voltage stacked- battery operation. the daisy-chain bus relays shutdown and alarm communication across up to 31 stacked modules without the need for isolation between each module. this results in a simplified system with reduced cost. the max11080 is ideal as an ultra-low-power, redundant cell fault monitor that is the perfect comple- ment to the max11068 high-voltage battery measure- ment ic. both ics in concert form a powerful li+ battery system monitor with redundant overvoltage and under- voltage fault detection. overvoltage and undervoltage fault detection figure 7 summarizes the fault-detection mechanism for a set of differential cell inputs in the max11080. first, the differential cell inputs are attenuated by a fac- tor of four while being level-shifted and converted to a single-ended voltage referenced to agnd. the ground-
referenced voltage is then connected to a set of over- voltage and undervoltage comparators. the threshold references for the comparators are set by the uvsel_ and ovsel_ input pins. when one of the cell voltages exceeds v ov or is below v uv when v uv is enabled, the internal cell out-of-range signal for the given cell is set and logically ored with the same signal for the other cell positions to create an overall out-of-range signal. when any cells are out-of-range as indicated by the internal out-of-range signal, an internal current source begins to charge the capacitor c dly connected to the cd pin. if the voltage at the cd pin reaches v cd , the alrm l line is set to v aa (+2.4v minimum as referred to agnd). normally, the alrm l line is a heartbeat signal with pulses occurring every 250?. if all cell voltages transition from out-of-range to in-range before the volt- age at pin cd reaches v cd , an internal switch clamps the cd pin to gnd. this action discharges c dly and, because the delay had not yet expired, no alarm occurs. discharging c dly ensures that the full delay time occurs for the next overvoltage or undervoltage event. figure 8 summarizes the c dly circuit. max11080 12-channel, high-voltage battery-pack fault monitor ______________________________________________________________________________________ 13 75mv hysteresis 75mv hysteresis short-circuit detector undervoltage comparator enable cell out-of-range 11 out-of-range v uv /4 v sc /4 v ov /4 v cell /4 v cell /4 v cell r shift r in * 40m ? typ 2m ? typ agnd + - + - v cell 6m ? typ + - v cell /(4 x r shift ) c n cells 2-12 cell 1 c n+1 hv figure 7. cell differential input and comparator block diagram 11 cell out-of-range 1 to 12 out-of-range v aa i cd 6.1 a v cd threshold alarm cd c dly 6k ? figure 8. c dly circuit block diagram
max11080 12-channel, high-voltage battery-pack fault monitor 14 ______________________________________________________________________________________ once the alrm l pin is forced high due to an alarm (+2.4v minimum as referred to agnd), it transitions back to a heartbeat signal only after all battery cells meet the following condition: (v ov - v hys ) > v cell(all) > (v uv + v hys ) examples of cell-voltage readings and their effect on the alarm status are shown in figures 9 and 10 for sin- gle- and multiple-cell systems. in the case where an upper module is forwarding an active alarm condition down the daisy chain, that condition continues to be propagated toward the host regardless of the alarm state of any lower module. furthermore, to circumvent the possibility of a short-circuited capacitor connected to cd preempting the fault-time validation process, a redundant built-in delay of 4s nominal is asserted as a backup. if the v cd threshold is not reached within 4s of an out-of-range event, the alarm becomes active. programmable delay time the alarm trigger delay time is calculated according to the following equations: t dly = (v cd x c dly )/i cd c dly = (t dly x i cd )/v cd the effective i cd value of the current source is 6.1? typical and the threshold voltage, v cd, is 1.23v typical. the vcd threshold is specified at an internal node prior to the resistor in series with the cd pin as shown in figure 8. the threshold voltage seen at the pin is approximately 1.18v due to the drop associated with the typical icd value and the 6k ? resistor. the max11080 can operate with capacitor values from 15nf (3.0ms) to 16.5? (3.32s). each capacitor should have a voltage tolerance of 5v minimum. cell-voltage threshold selection the overvoltage and undervoltage threshold selection is configured through the ovsel_ and uvsel_ inputs. the overvoltage selection can be configured from 3.3v to 4.8v in 100mv increments. the undervoltage thresh- old can be configured from 1.6v to 2.8v in 200mv increments. the undervoltage detection can also be disabled. see tables 1 and 2 for the proper configura- tion settings. immunity to unintended changes in the threshold volt- age setting (due to accidental pin-to-pin short circuits, for example) is provided. the customer-programmed selection is sensed and stored at power-up and any subsequent change to the input pin status is ignored. overvoltage selection threshold (v) ovsel3 ovsel2 ovsel1 ovsel0 3.3 0 0 0 0 3.4 0 0 0 1 3.5 0 0 1 0 3.6 0 0 1 1 3.7 0 1 0 0 3.8 0 1 0 1 3.9 0 1 1 0 4.0 0 1 1 1 4.1 1 0 0 0 4.2 1 0 0 1 4.3 1 0 1 0 4.4 1 0 1 1 4.5 1 1 0 0 4.6 1 1 0 1 4.7 1 1 1 0 4.8 1 1 1 1 table 1. overvoltage threshold selection
max11080 12-channel, high-voltage battery-pack fault monitor ______________________________________________________________________________________ 15 v ov v ov - v hys v cd cell voltage cd alrm l any cell figure 9. single-cell overvoltage detection example v ov v ov - v hys v cd cell voltage cell 12 cell 1 cell 11 cell n cd alrm l figure 10. multiple-cell overvoltage detection example
max11080 internal linear regulator the max11080 has an internal linear regulator for gen- erating the internal supply from dcin (figure 11). the regulator can accept a supply voltage on the dcin pin from +6.0v to +72v, which it regulates to 3.3v to run the voltage-detection system, control logic, and low- side alarm-pulse interface. when the shdn pin is not active and a sufficient voltage is applied to dcin, the output of the regulator becomes active. the regulator is paired with a power-on-reset (por) circuit that senses its output voltage and holds the max11080 in a reset state until the internal supply has reached a sustainable threshold of +3.0v (?%). the internal comparators have built-in hysteresis that can reject noise on the sup- ply line. because secondary metal batteries are never fully discharged to 0v, the max11080 is designed for a hot-swap insertion of the battery cells. once the por threshold is reached, approximately 1ms later the inter- nal reset signal disables, the internal oscillator starts, and the charge pump begins operating. the charge 12-channel, high-voltage battery-pack fault monitor 16 ______________________________________________________________________________________ undervoltage selection threshold (v) uvsel2 uvsel1 uvsel0 disabled 0 0 0 1.6 0 0 1 1.8 0 1 0 2.0 0 1 1 2.2 1 0 0 2.4 1 0 1 2.6 1 1 0 2.8 1 1 1 table 2. undervoltage threshold selection linear regulator +6.0v to +72v internal +3.3v charge pump +3.3v to gnd u +3.0v 5% bandgap reference die overtemperature detect dcin shdn v aa vdd u gnd u regulator enable charge-pump enable 35mv hysteresis por comparator internal por por threshold figure 11. internal linear regulator block diagram
max11080 12-channel, high-voltage battery-pack fault monitor ______________________________________________________________________________________ 17 por active voltage applied to dcin fault thresholds read 16khz oscillator enabled charge-pump enabled por cleared regulator enabled check shdn top board identified number of cells detected max11080 fully functional overvoltage comparator self-test check v aa shdn active v aa < 3.0v 1ms delay 3ms delay figure 12. linear regulator power-up sequence por inactive falling dcin voltage oscillator, charge pump, digital logic, and alarm pulse disabled por active check v aa v aa > 2.8v figure 13. low dcin por event pump reaches regulation in approximately 3ms. the max11080 associated with the top module in the bat- tery pack is identified as detailed in the topsel function section. this is followed by a self-test of the overvoltage comparators and detection of the number of cells connected. at this time in the power-on sequence, the max11080 is ready for operation. when the charge pump achieves regulation of 3.3v between vdd u and gnd u , it switches to a standby mode until the voltage drops by about 35mv. the specified accu- racy and full operation of the max11080 are not guar- anteed until a minimum of 6.0v is applied to the dcin pin. the linear regulator also incorporates a thermal shut- down feature. if the max11080 die temperature rises above +145?, the device shuts down. after a thermal shutdown, the die temperature must cool 15? below the shutdown temperature before the device restarts. figure 12 shows the linear regulator power-up sequence and figure 13 shows the low dcin por event.
max11080 dcin and gnd u supply connections a surge voltage is produced by the electric motor dur- ing regenerative braking conditions. the max11080 is designed to tolerate an absolute maximum of 80v under this condition. the max11080 should be protect- ed against higher voltages with an external voltage suppressor such as the pbmb78at3 on the dcin con- nection point. this protection circuit also helps to reduce power spikes that can occur during the inser- tion of the battery cells. during negative voltage excur- sions, the protection circuit stores enough charge to power the regulator through the transient. figure 14 shows the clamp configuration to protect the dcin sup- ply input. the dcin input contains a comparator circuit to detect an open circuit on this pin for fault-management pur- poses. whenever a nominal voltage of two silicon diode drops appears between c12 and dcin following the power-up sequence, the alrm l output is asserted as a fault indication. this voltage drop must appear for at least the delay time set by c dly to result in a fault. the voltage drop from c12 to dcin during normal operation should be kept at no more than 0.5v to prevent erro- neous tripping of the dcin open-circuit comparator under worst-case circumstances (lowest silicon diode forward bias voltage). the diode d dcin is used to sup- ply the transient current demanded at startup by the decoupling circuit. in parallel with this diode, r dcin provides the supply path during normal operation. it is selected to be 5k ? so that the maximum voltage drop between c12 and dcin is about 0.25v with nominal supply currents. high-power batteries are often used in noisy environ- ments subject to high dv/dt or di/dt supply noise and emi noise. for example, the supply noise of a power inverter driving a high horse-power motor produces a large square wave at the battery terminals, even though the battery is also a high-power battery. typically, the battery dominates the task of absorbing this noise, since it is impractical to put hundreds of farads at the inverter. the max11080 is designed with several mechanisms to deal with extremely noisy environments. first, the major power-supply inputs that see the full battery-stack volt- age are 80v tolerant. this is high enough to handle the large voltage changes on the battery stack that can occur when the batteries transition between charge and discharge conditions. next, the linear regulator has high psrr to produce a clean low-voltage power sup- ply for the internal circuitry. this allows dcin to be con- nected directly to the stack voltage. finally, gnd u serves two purposes. it supplies the internal charge pump with its power and acts as the reference ground for the upper alarm communication port. the charge pump creates a secondary low-voltage supply that is referenced to gnd u . because the level-shifted supply vdd u is referenced to gnd u , the entire upper alarm communication port glides smoothly on gnd u and it is effectively immune to noise on gnd u . the upper alarm signal is internally shifted down to agnd level where it is processed by the digital logic. there are two connec- tion methods that can be used for gnd u depending on application requirements. for the top module in a system, or where gnd u cannot be dc-coupled to the next higher module for other rea- sons, gnd u should be connected to the same location as dcin. this connection is valid as long as the voltage difference between the top of stack(n) and the bottom of stack(n+1) during worst-case conditions does not exceed the margin of the alarm pin signaling levels. when gnd u is not dc-coupled to the far side of the bus bar, it can be ac-coupled to the far side to main- tain alarm communication when the bus bar is open-cir- cuit. in that case, the two sides of the ac-coupling capacitor can be at different dc potentials, but the alarm communication signal continues to be passed across the capacitor connection. it is recommended that an ac- or dc-coupled version of gnd u is paired with the alarm signal through the communication bus wiring, possibly by twisted pair wire, for maximum noise immunity and minimum emissions. the preferred connection to reject noise between mod- ules is when a dc connection can be made from gnd u to agnd of the next module. it is again recommended that the dc-coupled gnd u signal is routed adjacent to the alarm signal as part of the communication bus for maximum noise immunity and minimum emissions. 12-channel, high-voltage battery-pack fault monitor 18 ______________________________________________________________________________________ to dcin input r dcin 5k ? c dcin 0.1 f 80v pbmb78at3 fuse top of cell stack see the application circuit diagrams (figures 15 and 16) for the proper connection location. figure 14. battery module surge and overvoltage protection circuit
max11080 12-channel, high-voltage battery-pack fault monitor ______________________________________________________________________________________ 19 c12 c11 c2 c1 c0 agnd dcin gnd u module n+1 c12 c11 c2 c1 c0 agnd dcin gnd u module n bus bar optional to maintain alarm communication figure 15. gnd u connection: ac-coupled to next module, dc-coupled to present module c12 c11 c2 c1 c0 agnd dcin gnd u module n+1 c12 c11 c2 c1 c0 agnd dcin gnd u module n bus bar communication bus figure 16. gnd u connection: dc-coupled with the communication bus
max11080 shutdown control the shdn pin connections of the max11080 operate in a manner that allows the shutdown/wake-up command to trickle up through the series of daisy-chained packs. because the internal linear regulator is powered down during shutdown, the shutdown function must operate when v aa is absent and it, therefore, cannot depend on a schmitt trigger input. a special low-current, high-volt- age circuit is used to detect the state of the shdn pin. the shutdown pin has a +1.8v minimum threshold for the inactive state. when shdn > 1.8v, the max11080 turns on and begins regulating vdd u and vdd l . if shdn < 0.6v, the max11080 shuts down. for automat- ic shutdown when the pack is removed from the sys- tem, connect a 200k ? resistor from shdn to agnd. once shdn is driven high, the power-up sequence fol- lows that described for the internal linear regulator. the shdn signal of the next higher module should be con- nected to vdd u through a 20k ? resistor pullup. this connection ensures that the next module in the daisy chain is enabled as vdd u of the lower module powers up. this action propagates up the daisy chain until the last battery module is enabled. the shutdown of a vdd u supply pulls the connected shdn pin of the upper module toward gnd l and propagates the shut- down signal up the daisy chain. a shutdown signal propagated from the first daisy- chain device to the last incurs a certain amount of delay. a deasserted shutdown signal is not propagated to the next higher module until the charge pump has regulated the level-shifted upper port supply, vdd u , to a value greater than the shdn v ih level. this time depends on both the charge-pump capacitor used and the value of the vdd u decoupling capacitor. a typical time delay of 10ms can be expected from the time the shdn pin reaches the deasserted state until vdd u reaches its full specified value. c1 input absolute maximum rating the c1 input is limited to v dcin - 0.6v above agnd or a maximum of 20v if the shdn pin is asserted. if an application requires that the 20v restriction be removed during active shutdown, then a 4.0v zener diode can be added from v aa to agnd. this protects v aa and allows the c1 input to go to v dcin - 0.6v regardless of the shdn state. it also allows the differential c1 to c0 voltage to range from -0.3v to +80v. cell-connection detection an individual max11080 can be connected to as many as 12 series-connected cells. to accommodate configu- rations with fewer cells, unused cell inputs must be short- ed together. the designer can choose which cell inputs to leave unused. the example application circuits in this document have chosen to populate the uppermost cell position and group the unused inputs just under this cell. at power-up, the part compares the voltage applied to each cell input with a nominal cell-detection threshold voltage of 0.7v. if the cell voltage is less than the cell- detection threshold, undervoltage detection is disabled for that cell input. if the voltage at the input is 0.7v or greater, undervoltage detection is specified by the state of the uvsel_ inputs. overvoltage detection is always enabled for all cell-voltage inputs. the cell-con- nection detection occurs just before the max11080 is fully functional as shown in figure 12 under ?umber of cells detected. topsel function the topsel pin is used to indicate to a device whether it is the top device in the daisy-chain stack. the top daisy-chain device is responsible for generating the heartbeat signal at the top of the alrm_ pin bus. this heartbeat propagates along the chain toward the host. to designate a device as the top device, the topsel pin should be connected to v aa . for all other devices in a daisy chain, this pin should be connected to agnd. the topsel pin has a weak internal pulldown resistor, but this resistor should not be relied upon as the sole means of setting the topsel logic level. the logic level of the topsel pin is not latched internally at startup and is continuously sampled during operation. the alrm u input should be connected to gnd u for the top module as good design practice to prevent noise pickup even though the input logic level is ignored. for the single device application, the device enters the ?evel?mode when the topsel is connected to agnd. the alrm l shows the level of agnd for no alarm state and vaa for alarm state. alrm u has to be tied to gnd u for this mode. the following table summarizes the operation of topsel and alrm l : internal self-test the max11080 performs an internal self-test during power-up according to the linear regulator power-up flowchart (figure 12). each overvoltage comparator is tested for the ability to detect an internally generated overvoltage test condition. this is done by using the ground voltage level as the threshold reference in place of the usual threshold level. figure 8 shows the connec- 12-channel, high-voltage battery-pack fault monitor 20 ______________________________________________________________________________________ alrm l topsel alrm u no alarm alarm 00 0 1 1x heartbeat 1
tion for this test-mode compare level. if all comparators can detect the internally generated overvoltage test event, part operation continues. if any comparator fails to detect the internally generated overvoltage test event, a fault is signaled using the alrm l pin. the device must be power cycled to retest the comparators and attempt to clear this fault condition. failure mode and effects analysis high-voltage battery-pack systems can be subjected to severe stresses during in-service fault conditions and could experience similar conditions during the manu- facturing and assembly process. the max11080 is designed with high regard to these potential states. open and short circuits at the package level must be readily detected for fault diagnosis and should be toler- ated whenever possible. a number of circuits are employed within the max11080 specifically to detect such conditions and progress to a known device state. table 3 summarizes other conditions typical in a normal manufacturing process along with their effect on the max11080 device. see table 4 for the fema analysis of the max11080. if the cell voltage is within the monitor range, the heart- beatsignal on the alrml resumes once the fault condi- tion (either open or short) is removed, unless specified. max11080 12-channel, high-voltage battery-pack fault monitor ______________________________________________________________________________________ 21 condition effect design recommendation pcb or ic package open or short circuit no stack load refer to the pin-level fmea analysis spreadsheet available from the factory the built-in features of the max11080 should ensure low fmea risk in most cases. random connection of cells to ic no stack load no effect the series resistors on the cell inputs of the max11080 as well as the internal design ensure protection against random power supply or ground connections. random connection of modules no stack load no effect each module is referenced to its neighbor, so no special connection order is necessary. random connect/disconnect of communication busno stack load; ac- or dc-coupled communication from host to the first break in the daisy-chain bus the level-shifted interface design of the max11080 ensures that the shdn , gnd u , and alrm_ communication bus can be connected at any time with no load. random connect/disconnect of communication buswith stack load; ac- or dc-coupled communication from host to the first break in the daisy-chain bus the level-shifted interface design of the max11080 ensures that the shdn , gnd u , alrm_ communication bus can be connected at any time as long as the power bus is properly connected. connect/disconnect module interconnect (bus bar)no stack load no effect for dc- or ac-coupled communication bus a break in the power bus does not cause a problem as long as there is no load on the stack. removal/fault of module interconnect (bus bar)with stack load no effect for ac-coupled communication bus; device damage for dc-coupled bus an ac-coupled bus with isolation on the shdn pin or a redundant bus-bar connection should be used to protect against this case. removal/fault of module interconnect (bus bar)with stack under charge no effect for ac-coupled communication bus; device damage for dc-coupled bus an ac-coupled bus with isolation on the shdn pin or a redundant bus-bar connection should be used to protect against this case. table 3. system fault modes
max11080 12-channel, high-voltage battery-pack fault monitor 22 ______________________________________________________________________________________ pin number name action effect open (or disconnected) alrm l goes high (see note 6). 1 dcin short to pin 2 alrm l goes high. open (or disconnected) alrm l goes high. 2hv short to pin 3 no effect. open (or disconnected) no effect. 3n.c. short to pin 4 no effect. open (or disconnected) ? if open occurs before power-up, the part works as if c12 does not exist because the internal circuit detects the situation and assumes it is what the application intended to do. the monitoring of c12 to c11 is disabled and is not enabled even if the pin is reconnected. ? if open occurs after power-up, it is considered a zero voltage input. alrm l goes high when the undervoltage is enabled. 4 c12 short to pin 5 ? if short occurs before power-up, the part works as if c12 does not exist because the internal circuit detects the situation and assumes it is what the application intended to do. the monitoring of c12 to c11 is disabled and is not enabled even if the short is removed. ? if short occurs after power-up, the situation is treated as a zero voltage input for c12 to c11. alrm l goes high when the undervoltage is enabled. open (or disconnected) alrm l goes high because it causes an overvoltage to the affected input pair even if the overvoltage is set to the maximum. 5 c11 short to pin 6 ? if short occurs before power-up, the part works as if c11 does not exist because the internal circuit detects the situation and assumes it is what the application intended to do. the monitoring of c11 to c10 is disabled and is not enabled even if the short is removed. ? if short occurs after power-up, the situation is treated as a zero voltage input for c11 to c10. alrm l goes high when the undervoltage is enabled. open (or disconnected) alrm l goes high as it causes an overvoltage to the affected input pair even if the overvoltage is set to the maximum. 6 c10 short to pin 7 ? if short occurs before power-up, the part works as if c10 does not exist because the internal circuit detects the situation and assumes it is what the application intended to do. the monitoring of c10 to c9 is disabled and is not enabled even if the short is removed. ? if short occurs after power-up, the situation is treated as a zero voltage input for c10 to c9. alrm l goes high when the undervoltage is enabled. open (or disconnected) alrm l goes high as it causes an overvoltage to the affected input pair even if the overvoltage is set to the maximum. 7c9 short to pin 8 ? if short occurs before power-up, the part works as if c9 does not exist because the internal circuit detects the situation and assumes it is what the application intended to do. the monitoring of c9 to c8 is disabled and is not enabled even if the short is removed. ? if short occurs after power-up, the situation is treated as a zero voltage input for c9 to c8. alrm l goes high when the undervoltage is enabled. table 4. fema analysis (note 5)
max11080 12-channel, high-voltage battery-pack fault monitor ______________________________________________________________________________________ 23 pin number name action effect open (or disconnected) alrm l goes high as it causes an overvoltage to the affected input pair even if the overvoltage is set to the maximum. 8c8 short to pin 9 ? if short occurs before power-up, the part works as if c8 does not exist because the internal circuit detects the situation and assumes it is what the application intended to do. the monitoring of c8 to c7 is disabled and is not enabled even if the short is removed. ? if short occurs after power-up, the situation is treated as a zero voltage input for c8 to c7. alrm l goes high when the undervoltage is enabled. open (or disconnected) alrm l goes high as it causes an overvoltage to the affected input pair even if the overvoltage is set to the maximum. 9c7 short to pin 10 ? if short occurs before power-up, the part works as if c7 does not exist because the internal circuit detects the situation and assumes it is what the application intended to do. the monitoring of c7 to c6 is disabled and is not enabled even if the short is removed. ? if short occurs after power-up, the situation is treated as a zero voltage input for c7 to c6. alrm l goes high when the undervoltage is enabled. open (or disconnected) alrm l goes high as it causes an overvoltage to the affected input pair even if the overvoltage is set to the maximum. 10 c6 short to pin 11 ? if short occurs before power-up, the part works as if c6 does not exist because the internal circuit detects the situation and assumes it is what the application intended to do. the monitoring of c6 to c5 is disabled and is not enabled even if the short is removed. ? if short occurs after power-up, the situation is treated as a zero voltage input for c6 to c5. alrm l goes high when the undervoltage is enabled. open (or disconnected) alrm l goes high as it causes an overvoltage to the affected input pair even if the overvoltage is set to the maximum. 11 c5 short to pin 12 ? if short occurs before power-up, the part works as if c5 does not exist because the internal circuit detects the situation and assumes it is what the application intended to do. the monitoring of c5 to c4 is disabled and is not enabled even if the short is removed. ? if short occurs after power-up, the situation is treated as a zero voltage input for c5 to c4. alrm l goes high when the undervoltage is enabled. open (or disconnected) alrm l goes high as it causes an overvoltage to the affected input pair even if the overvoltage is set to the maximum. 12 c4 short to pin 13 ? if short occurs before power-up, the part works as if c4 does not exist because the internal circuit detects the situation and assumes it is what the application intended to do. the monitoring of c4 to c3 is disabled and is not enabled even if the short is removed. ? if short occurs after power-up, the situation is treated as a zero voltage input for c4 to c3. alrm l goes high when the undervoltage is enabled. table 4. fema analysis (note 5) (continued)
max11080 12-channel, high-voltage battery-pack fault monitor 24 ______________________________________________________________________________________ pin number name action effect open (or disconnected) alrm l goes high as it causes an overvoltage to the affected input pair even if the overvoltage is set to the maximum. 13 c3 short to pin 14 ? if short occurs before power-up, the part works as if c3 does not exist because the internal circuit detects the situation and assumes it is what the application intended to do. the monitoring of c3 to c2 is disabled and is not enabled even if the short is removed. ? if short occurs after power-up, the situation is treated as a zero voltage input for c5 to c4. alrm l goes high when the undervoltage is enabled. open (or disconnected) alrm l goes high as it causes an overvoltage to the affected input pair even if the overvoltage is set to the maximum. 14 c2 short to pin 15 ? if short occurs before power-up, the part works as if c2 does not exist because the internal circuit detects the situation and assumes it is what the application intended to do. the monitoring of c2 to c1 is disabled and is not enabled even if the short is removed. ? if short occurs after power-up, the situation is treated as a zero voltage input for c2 to c1. alrm l goes high when the undervoltage is enabled. open (or disconnected) alrm l goes high as it causes an overvoltage to the affected input pair even if the overvoltage is set to the maximum. 15 c1 short to pin 16 alrm l goes high irrespective of whether undervoltage is enabled/disabled and before and after power-up. open (or disconnected) alrm l goes high irrespective of whether undervoltage is enabled/disabled and before and after power-up. 16 c0 short to pin 17 ? alrm l goes high if pin 17 is pulled high by v aa . the part consumes a large current as v aa is shorted to agnd (connected to c0). ? if pin 17 is tied to agnd, there is no effect. open (or disconnected) the pin defaults to low due to the internal pulldown (see note 7). the effect depends on the intended undervoltage setting. 17 uvsel0 short to pin 18 ? if pin 17 and pin 18 have the same intended value, there is no effect for the short. ? if pin 17 and pin 18 have a different setting, the v aa is shorted to agnd. alrm l goes low. open (or disconnected) the pin defaults to low due to the internal pulldown (see note 7). the effect depends on the intended undervoltage setting. 18 uvsel1 short to pin 19 ? if pin 18 and pin 19 have the same intended value, there is no effect for the short. ? if pin 18 and pin 19 have a different setting, the v aa is shorted to agnd. alrm l goes low. open (or disconnected) the pin defaults to low due to the internal pulldown (see note 7). the effect depends on the intended undervoltage setting. 19 uvsel2 short to pin 20 ? if pin 19 and pin 20 have the same intended value, there is no effect for the short. ? if pin 19 and pin 20 have the different setting, the v aa is shorted to. agnd alrm l goes low. table 4. fema analysis (note 5) (continued)
max11080 12-channel, high-voltage battery-pack fault monitor ______________________________________________________________________________________ 25 pin number name action effect open (or disconnected) the pin defaults to low due to the internal pulldown (see note 7). the effect depends on the intended overvoltage setting. 20 ovsel0 short to pin 21 ? if pin 20 and pin 21 have the same intended value, there is no effect for the short. ? if pin 20 and pin 21 have a different setting, the v aa is shorted to agnd. alrm l goes low. open (or disconnected) the pin defaults to low due to the internal pulldown (see note 7). the effect depends on the intended overvoltage setting. 21 ovsel1 short to pin 22 ? if pin 21 and pin 22 have the same intended value, there is no effect for the short. ? if pin 21 and pin 22 have a different setting, the v aa is shorted to agnd. alrm l goes low. open (or disconnected) the pin defaults to low due to the internal pulldown (see note 7). the effect depends on the intended overvoltage setting. 22 ovsel2 short to pin 23 ? if pin 22 and pin 23 have the same intended value, there is no effect for the short. ? if pin 22 and pin 23 have a different setting, the v aa is shorted to agnd. alrm l goes low. open (or disconnected) the pin defaults to low due to the internal pulldown (see note 7). the effect depends on the intended overvoltage setting. 23 ovsel3 short to pin 24 ? if pin 23 is set high, there is no effect for the short. ? if pin 23 is set low, the v aa is shorted to agnd. alrm l goes low. open (or disconnected) alrm l goes high. 24 v aa short to pin 25 alrm l goes low. open (or disconnected) v aa goes to approximately 100mv and alrm l is approximately 0.5v. there is no heartbeat if there is a one before the opening. 25 agnd short to pin 26 the device is in shutdown mode. alrm l is low. open (or disconnected) the pin is internally pulled down and the device goes to the shutdown mode. alrm l is low. 26 shdn short to pin 27 alrm l goes high and stays high even if the short is removed. the internal detect circuit considers this a major failure and the part has to be repowered up to come out of this state. open (or disconnected) the signal at the alrm l cannot be seen by the host. 27 alrm l short to pin 28 alrm l goes high and stays high even if the short is removed. the internal detect circuit considers this a major failure and the part has to be repowered up to come out of this state. open (or disconnected) the delay between the fault condition and alarm setting (alrm l goes high) goes to the minimum. this means there is almost no delay. 28 cd short to pin 29 the delay between the fault condition and alarm setting (alrm l goes high) is approximately 4s, which is set by the internal watchdog. table 4. fema analysis (note 5) (continued)
max11080 12-channel, high-voltage battery-pack fault monitor 26 ______________________________________________________________________________________ pin number name action effect open (or disconnected) no effect. 29 agnd short to pin 30 no effect. open (or disconnected) no effect. 30 agnd short to pin 31 if pin topsel is set high (v aa ), it causes the short between v aa and agnd. alrm l is low. there is no effect if topsel is set low. open (or disconnected) if the part is the topmost device in the daisy chain, the alrm l is set high as the state of topsel is low (internally pulled down). there are no other effects as the state of the pin stays the same (both low). 31 topsel short to pin 32 no effect if topsel is set low. if topsel is set high, it causes the short between v aa and agnd and alrm l is low. open (or disconnected) no effect. 32 agnd short to pin 33 no effect. open (or disconnected) no effect. 33 n.c. short to pin 34 no effect. open (or disconnected) alrm u is internally pulled up to vdd u . there is no effect to the topmost device. otherwise, the communication of the chain is broken and the alarm signal from the parts close to the topmost device are not passed through. since alrm l is a reflection of alrm u , the state of alrm l is high for the no- alarm state. 34 alrm u short to pin 35 no effect for the topmost device. otherwise, the communication of the chain is broken and the alarm signal from the parts close to the topmost are not passed through. since alrm l is a reflection of alrm u , the state of alrm l is low for the no-alarm state. open (or disconnected) the alrm l goes high. vdd u floats down approximately 4v. (see note 8.) 35 gnd u short to pin 36 the alrm l is high. (see note 8). open (or disconnected) alrm l goes high. hv is approximately 0.4v below dcin. (see note 8.) 36 vdd u short to pin 37 alrm l goes high. vdd u is approximately 0.5v lower than gnd u . (see note 8.) open (or disconnected) alrm l goes high. vdd u and hv collapse. 37 cp- short to pin 38 alrm l goes high. vdd u is approximately 0.5v lower than gnd u . (see note 8.) 38 cp+ open (or disconnected) alrm l goes high. vdd u and hv collapse. (see note 8.) table 4. fema analysis (note 5) (continued) note 5: if the cell voltage is within the monitor range, the heartbeat signal on the alrml resumes once the fault condition is removed. note 6: the voltage level of high is equal to v aa and low is equal to agnd. note 7: even if the pin has internal pulldown, the pulldown is very weak and the pin should be tied to agnd for logic 0 setting. note 8: vdd u - gnd u = 3.3 - v and hv - dcin = 3.6v for the typical configuration. when vdd u and hv collapse, vdd u - gnd u 0 - v and hv - dcin -0.4v.
max11080 12-channel, high-voltage battery-pack fault monitor maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 27 2009 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. top view tssop max11080 35 4 gnd u c12 36 3 vdd u n.c. 37 2 cp- hv 38 1 cp+ dcin 32 7 agnd c9 33 6 n.c. c10 31 8 topsel c8 30 9 agnd c7 29 10 agnd c6 28 11 cd c5 27 12 alrm l c4 34 5 alrm u c11 25 14 agnd c2 24 v aa 15 c1 23 ovsel3 16 c0 22 ovsel2 17 uvsel0 21 ovsel1 18 uvsel1 20 ovsel0 19 uvsel2 26 13 shdn c3 + pin configuration package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . package type package code document no. 38 tssop u38-1 21-0081

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